1. Field of the Invention
The present invention relates to a plasma display apparatus and driving method thereof.
2. Background of the Related Art
A plasma display panel (hereinafter, referred to as a “PDP”) displays images including characters and/or graphics by light-emitting phosphors with ultraviolet rays generated during the discharge of an inert gas such as He+Xe, Ne+Xe or He+Ne+Xe. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology.
Referring to FIGS. 1 and 2, a three-electrode AC surface discharge type PDP comprises scan electrodes Y1 to Yn and sustain electrodes Z formed on a bottom surface of an upper substrate 10, and address electrodes X1 to Xm formed on a top surface of a lower substrate 18.
Discharge cells 1 of the PDP are formed at the intersections of the scan electrodes Y1 to Yn and the address electrodes X1 to Xm, and the sustain electrodes Z and the address electrodes X1 to Xm. Each of the scan electrodes Y1 to Yn and the sustain electrodes Z comprises a transparent electrode 12, and a metal bus electrode 11, which has a line width narrower than that of the transparent electrode 12 and is disposed at one side edge of the transparent electrode. The transparent electrode 12 is generally formed of Indium Tin Oxide (ITO) and is formed on the bottom surface of the upper substrate 10. The metal bus electrode is generally formed of metal and is formed on the transparent electrode 12. The metal bus electrode functions to reduce a voltage drop incurred by the transparent electrode 12 with high resistance.
An upper dielectric layer 13 and a protection layer 14 are laminated on the bottom surface of the upper substrate 10 in which the scan electrodes Y1 to Yn and the sustain electrodes Z. Wall charges generated during the discharge of plasma are accumulated on the upper dielectric layer 13. The protection layer 14 serves to prevent the electrodes Y1 to Yn and Z and the upper dielectric layer 13 from sputtering generated during the discharge of plasma, and enhance emission efficiency of secondary electrons. Magnesium oxide (MgO) is generally used as a material of the protection layer 14.
The address electrodes X1 to Xm are formed on the lower substrate 18 in such a way as to cross the scan electrodes Y1 to Yn and the sustain electrodes Z. A lower dielectric layer 17 and barrier ribs 15 are formed on the lower substrate 18. A phosphor layer 16 is formed on surfaces of the lower dielectric layer 17 and the barrier ribs 15. The barrier ribs 15 are formed parallel to the address electrodes X1 to Xm to physically divide the discharge cells and preclude ultraviolet rays generated upon discharge and a visible ray from leaking to neighboring discharge cells. The phosphor layer 16 is excited and light-emitted with ultraviolet rays generated during the discharge of plasma discharge, thus generating any one of red, green and blue visible rays.
An inert mixed gas, such as He+Xe, Ne+Xe or He+Ne+Xe, is injected into discharge spaces of the discharge cells, which are provided between the upper substrate 10 and the barrier ribs 15 and between the lower substrate 18 and the barrier ribs 15.
This PDP is driven with one frame being time-divided into several sub-fields having a different number of emission in order to implement gray scales of images. For example, if it is sought to display images with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60 seconds is divided into eight sub-fields (SF1 to SF8). Each of the eight sub-fields (SF1 to SF8) is divided into a reset period for initializing discharge cells, an address period for selecting discharge cells and a sustain period for implementing gray scales depending on the number of discharge. The reset period and the address period of each of the sub-fields (SF1 to SF8) are the same every sub-field, whereas the sustain period and the number of discharges increase in the ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field.
Meanwhile, in the case where charge/discharge is generated in the PDP, there is almost no energy consumption only with capacitive load within the PDP. However, lots of energy loss is generated since a driving signal is generated with switching of AC power. More particularly, if excessive current flows within the discharge cell, energy loss is further increased. Such energy loss results in a raised temperature of switching elements. In the worst case, the raised temperature may break the switching elements. To recover energy that is unnecessarily generated within the panel, the driving circuit of the PDP comprises an energy recovery circuit as shown in FIG. 3.
Referring to FIG. 3, the energy recovery circuit comprises an inductor L that resonates along with a capacitive load Cp of the PDP, an external capacitor Cex for storing a voltage recovered from the capacitive load Cp of the PDP, switching elements S1 to S4 for switching a current path, and diodes D1, D2 for precluding an inverse current.
The capacitive load Cp of the PDP is formed between two electrodes in which a discharge is generated within each discharge cell. In FIG. 3, reference numeral “Re” equivalently indicates wiring resistance formed between the energy recovery circuit and the electrodes of the PDP. Reference numeral “R_Cp” equivalently indicates parasitic resistance existing in the discharge cell of the PDP. In addition, reference numeral “Vs” indicates an external sustain DC power source. The switching elements S1 to S4 are implemented using a semiconductor switching element such as a MOS FET element.
The operation of the energy recovery circuit constructed above will be described with reference to FIG. 4. FIG. 4 is a view for illustrating control signals of the energy recovery circuit and a voltage in each node according to each of the control signals. The external capacitor Cex is charged with a voltage as much as Vs/2 in an initial condition.
Referring to FIGS. 3 and 4, during a period t1, the first switching element S1 is closed according to the control signal (Er-up) from a timing controller (not shown) and is thus turned on. The remaining switching elements S2 to S4 keep turned off. At this time, electric charges stored in the external capacitor Cex are supplied to the inductor L via the first switching element S1 and the first diode D1. The inductor L constructs a serial LC resonant circuit along with the capacitive load Cp of the PDP. Therefore, at the period t1, the PDP starts being charged with a LC resonant waveform.
During a period t2, the first switching element S1 keeps turned on. The third switching element S3 is turned on in response to the control signal (Sus-up) from the timing controller. The second and fourth switching elements S3, S4 keep turned off. The capacitive load Cp of the PDP is charged with a sustain voltage (Vs), which is received via the third switching element S3. During the period t2, the capacitive load Cp of the PDP is kept to the sustain voltage (Vs).
During a period t3, the second switching element S2 is turned on, the fourth switching element S4 keeps turned off, and the first and third switching elements S1, S3 are turned off, in response to the control signal (Er-dn) from the timing controller. Therefore, invalid power from the capacitive load Cp of the PDP are recovered by the external capacitor Cex through the inductor L, the second diode and the second switching element S2.
During a period t4, the fourth switching element S4 is turned on, the second switching element S2 is turned off, and the first and third switching elements S1, S3 keep turned off, in response to the control signal (Sus-dn) from the timing controller. The capacitive load Cp of the PDP is discharged up to a base voltage (GND).
The operation of the second switching element of the switching elements forming the current path so that such an operation is performed will be described as follows.
FIG. 5 shows a bias circuit of the second switching element.
FIGS. 6a to 6c show a gate signal (FIG. 6b) and a Vgs (FIG. 6c) value depending on the application of a control signal (FIG. 6a) in the timing controller.
Referring to FIG. 5, the bias circuit of the second switching element ER-DN comprises a Zener diode ZD, which is connected between a first node n1 between a timing controller T/C and the gate terminal of the switching element and a second node n2 between the external capacitor Cex and the switching element. Between the first node n1 and the second node n2 is further provided a resistor R connected to the Zener diode ZD in parallel in order to prevent overload of the Zener diode. The Zener diode ZD generates a constant voltage of 15V if a current of an inverse direction flows through the first node n1 and the second node n2.
Referring to FIGS. 5 and 6, if a low signal (GND) is applied to the second switch in the timing controller T/C, a third node n3 has a voltage of Vs/2, which is charged by an external capacitor C. Since the second switch S2 is turned off, a voltage value of the gate terminal also has Vs/2. If a high signal of 15V is applied as the control signal during the period T1, a voltage value of the gate terminal becomes (Vs/2)+15V, and Vgs becomes 15V since it is a difference in a voltage value between the gate terminal and the source terminal.
As can be seen from the above operation, in the case where the low signal (GND) is applied from the timing controller to the third switching element, the value of Vgs must have 0V as shown in FIG. 6c. However, even when the low signal (GND) is applied as the control signal, an unwanted voltage may be generated from the second switching element. This will be described below with reference to FIG. 7, which shows a voltage value in the first node n1 and the second node n2 depending on the same timing shown in FIG. 4.
From FIG. 7, it can be seen that a voltage value at the first node n1 is abruptly varied at the start point and the end point of t1. The current is the amount of variation in a voltage according to a time. When the amount of variation in a voltage increases, an induced current is generated. This induced current generates an instant noise voltage within the second switching element whose Vgs value must be 0V during the period t1. This noise voltage generates, which may reduce and/or break the lifespan of the element. Furthermore, if the noise voltage exceeds Vth (3 to 5V), the switching element is operated to generate a malfunction.